Chips You Can Rewire
FPGA Mining Explained, from Spartan-6 to VU9P

Chapter I: A little argument on Discord

It began, as most things in crypto do, with a chat channel. We had just published our FPGA bitstream for Proxima, and somebody asked the perfectly reasonable question: “Isn’t a GPU just much better and more efficient?” Somebody else admitted they had never owned an FPGA and that it all looked frightfully complicated.

Both fair points, and both worth a proper answer rather than a one-line reply between two walls of text about pool advertising. So here it is: what these things are, where they came from, why they can be so efficient, and, just as importantly, where they are completely the wrong tool. We will try to keep the jargon on a short lead.

Chapter II: So what actually is an FPGA?

FPGA stands for Field-Programmable Gate Array. Unpack that and it is rather literal: an array of logic gates that you can program “in the field”, meaning after the chip has left the factory.

A CPU or GPU is a fixed circuit that runs software: it fetches instructions one after another and executes them. An FPGA doesn’t run instructions at all. It is a huge grid of small building blocks with a programmable telephone exchange in between, and you decide how the blocks are wired together. Once wired, data simply flows through the circuit you built.

The building blocks are:

• Lookup tables (LUTs): tiny memories that can impersonate any logic function of a handful of inputs. AND, XOR, a bit of an adder: a LUT will happily be any of them.
• Flip-flops: one-bit storage cells that hold results from one clock tick to the next. They are what let you build pipelines.
• DSP slices: hard-wired multipliers and adders for heavy arithmetic.
• Block RAM (and on newer chips UltraRAM): small on-chip memories, a few megabytes on a mid-range part and a few tens of megabytes on a big one. Remember this number; it matters later.
• Routing: the programmable wiring that connects all of the above. On a big FPGA the routing takes up more silicon than the logic does.

And the bitstream?

The bitstream is the file that sets every one of those switches. You describe your circuit in a hardware description language such as Verilog or VHDL. Then the vendor tools synthesise it into LUTs and flip-flops, place every piece somewhere on the chip, route the wires between them, and finally check that every signal arrives in time for the next clock tick. That last step is called timing closure, and it is where FPGA engineers age visibly.

Load the bitstream (over USB on a ZTEX board, over JTAG on a VU9P card) and a blank chip becomes, say, a row of BLAKE2b cores. Load a different one and the same chip becomes a SHA-3 miner, a video encoder or a radar filter. It is the electronic equivalent of a Meccano set that rebuilds itself in under a minute.

What are FPGAs normally used for?

Mining is a sideshow. The day jobs are far more respectable:

• Telecoms: mobile base stations and network switches, where standards change faster than anyone can tape out a chip.
• High-frequency trading: when nanoseconds are worth money, you put the trading logic straight onto the network card.
• Aerospace and defence: radar, satellites and avionics, where small volumes make custom chips uneconomical.
• Test and measurement: the insides of oscilloscopes and logic analysers.
• Datacentre acceleration: Microsoft famously put FPGAs into its servers to speed up Bing, and Amazon rents out VU9P chips by the hour as EC2 F1 instances. Yes, the same chip family we mine Proxima on.
• Retro gaming: projects like MiSTer re-create old consoles and home computers in hardware rather than emulating them in software. Your Commodore 64 lives on, in gates.
• Building ASICs, which deserves a chapter of its own.

Chapter III: Every ASIC starts life as an FPGA

An ASIC (Application-Specific Integrated Circuit) is a chip designed to do one thing. A Bitcoin ASIC does SHA-256 and absolutely nothing else, which is precisely why it is so good at it. The catch is the cost of getting there. A modern tape-out means photomasks, engineering runs and months of fab time, adding up to millions of dollars on a leading-edge process, and if there is a bug in the silicon you get to pay all of it again.

So nobody sensible sends a design to the fab untested. The same Verilog that will become the ASIC is first run on FPGAs: on a single board for a small design, or on huge racks of them for a phone processor. The big chip-design companies sell entire “prototyping” and emulation systems built from FPGAs for exactly this purpose. You find bugs at FPGA prices instead of at fab prices, and the software team can start writing drivers months before real silicon exists.

Mining hardware followed exactly this path. The SHA-256 cores that ran on FPGAs in 2011 and 2012 were, in spirit and often in actual source code, the prototypes of the first Bitcoin ASICs. Butterfly Labs sold FPGA miners before its ASICs; the hobbyist designs proved the pipeline, and the ASIC makers then “froze” it into silicon.

That “flexibility tax” is well documented in the academic literature: the classic measurements put an FPGA at very roughly 20–35× the silicon area, around 10–15× the dynamic power and 3–4× slower than the same circuit as an ASIC. Which raises the obvious question: if FPGAs pay such a heavy tax, how on earth do they beat GPUs?

Chapter IV: Why a good bitstream beats a GPU per watt

Because a GPU pays a tax too, and on the right algorithm it is an even bigger one.

A GPU is a magnificent general-purpose parallel computer. Every cycle, each of its tens of thousands of cores fetches an instruction, decodes it, schedules it, reads operands from a register file, does the actual sum, and writes the result back. Only that one step, the actual sum, is hashing. Everything else is overhead, and moving data in and out of register files and caches costs far more energy than the arithmetic itself. A GPU is a symphony orchestra that has to read the whole score aloud before playing each note.

A miner on an FPGA has no instructions to fetch. The hash function is the circuit. Each round of the algorithm becomes a stage of physical logic, the stages are chained into a pipeline, and every clock tick a new nonce goes in at one end while a finished hash drops out of the other. There is no instruction decoding, no scheduler and no register file traffic, just data flowing through gates.

The BLAKE2b example: where the free lunch is a free rotation

Proxima’s proof of work is BLAKE2b, and it shows the difference beautifully. BLAKE2b works on 64-bit words using only three operations: addition, XOR and bit rotation (by 32, 24, 16 and 63 bits). Now look at what each kind of chip has to do:

• On a GPU, the integer units are 32 bits wide. Every 64-bit addition becomes two 32-bit additions plus carry handling, and every 64-bit rotation becomes a pair of shift operations. Each one is an instruction, and each instruction has the overhead described above.
• On an FPGA, a 64-bit adder is built straight into the fabric using the chip’s dedicated carry chains. And a rotation by a fixed amount costs nothing at all. It isn’t a calculation: you simply connect wire 0 to where wire 24 should go. Zero logic, zero power, zero clock cycles. Somewhere a GPU is quietly weeping.

Add to that the fact that you can size the circuit exactly to the job (no 32-bit lanes doing 8-bit work, no idle floating-point units) and you get a chip where nearly every switching transistor is doing useful hashing. That is the whole trick.

The honest numbers

Here is where we have to be scrupulously fair, because the chip’s age matters enormously. Manufacturing process (the “nm” figure) is the single biggest factor in energy efficiency, and our FPGAs are not young.

Our own measurements with ProxiChorizo (GPU) and suprminer-fpga (FPGA). The ZTEX figure is the 124 MHz bitstream; the bundled 100 MHz proof of concept does about 100 MH/s. MH/J = megahashes per joule, i.e. per watt-second.

Read that table carefully, because it says two different things.

First, the old Spartan-6 board is not more efficient than a modern GPU. It does about a quarter of the 5090’s hashes per watt. But consider what it is: a 45 nm chip designed in 2009, four or five process generations behind, and it still gets within a factor of four of NVIDIA’s current flagship. That is like a 1960s Mini keeping up with a modern hatchback on fuel economy. It isn’t winning, but it really shouldn’t be in the race at all. It also draws 25 W, runs off USB, sits silently on a shelf and needs no 1,000 W power supply or space heater licence.

Second, a modern FPGA beats the GPU outright. The VU9P is itself ten years old and three process generations behind the 5090, yet it delivers about twice the hashes per watt. Put the two on the same process node and the gap would be wider still. That is the architectural advantage, plain and simple, once someone has done the hard work of building a bitstream that closes timing at a decent clock.

Chapter V: A short history, or when a shelf of blinking boards ruled Bitcoin

2009–2010: CPUs, then GPUs

Bitcoin was first mined on ordinary CPUs. Within about eighteen months people realised that graphics cards were far better at SHA-256, and Radeon HD 5870s and 5970s became the workhorses, managing a few hundred MH/s each while doubling as rather effective radiators.

2011: the FPGA arrives

In 2011 open-source SHA-256 designs for FPGAs started appearing on BitcoinTalk, first on development boards and then on purpose-built mining boards. By far the most popular chip was the Xilinx Spartan-6 LX150: cheap for its size, plenty of logic, and modest power. It was the right chip at the right time.

Out of that came a small zoo of boards that old-timers still speak of with misty eyes:

• ZTEX USB-FPGA 1.15x and 1.15y from Germany: one or four LX150s with a USB controller, roughly 210 MH/s per chip on SHA-256, so about 860 MH/s for the quad 1.15y. Plug-and-play by the standards of the day, and the board we still mine Proxima on.
• Cairnsmore1 from Enterpoint in Malvern, England: a quad-LX150 board that put out around 800 MH/s and could be clocked higher. A British mining board, which is reason enough for us to mention it with some pride and a biscuit.
• Icarus: a dual-LX150 open-hardware design from China, around 380 MH/s.
• X6500: another dual-LX150 board at roughly 400 MH/s.
• Butterfly Labs’ BFL Single: around 830 MH/s in a box with a fan that could be heard in the next county.

The appeal was efficiency. A Radeon did about 2–3 MH/J on SHA-256; a Spartan-6 board managed somewhere around 20. Ten times the hashes for the same electricity, near silence and no house fires. cgminer and later BFGMiner grew drivers for most of these boards, and for about eighteen glorious months the serious miners were the ones with a shelf of blinking FPGA boards.

2013: the ASIC tide comes in

Then, in early 2013, the first Bitcoin ASICs shipped. Avalon, ASICMiner’s Block Erupters, and eventually Butterfly Labs’ own long-delayed chips: the FPGA SHA-256 cores had been frozen into silicon, and suddenly a USB stick did what a whole FPGA board did. Exactly as Chapter III predicts, the FPGA had been the prototype, and once the ASIC arrived the prototype was obsolete for that algorithm. Thousands of Spartan-6 boards went into drawers, lofts and the odd shed.

2017–2020: the big iron years

FPGAs came back for altcoins, and this time in datacentre form. The star was the Xilinx Virtex UltraScale+ VU9P, a 16 nm monster with roughly 1.2 million logic cells. It turned up in Amazon’s F1 cloud instances and, more importantly for miners, in PCIe cards such as the VCU1525 development board and its mining-flavoured cousin the BCU1525. Later came even bigger parts such as the VU13P in Squirrel Research Labs’ CVP-13.

Squirrel (SQRL) also made the cheerful little Acorn boards: Artix-7 FPGAs on M.2 cards that you could tuck into a spare slot. A whole cottage industry grew up around them: bitstream developers selling algorithm images, often with a dev fee, for coins whose algorithms had no ASIC yet. Some coins even went the other way and designed for FPGAs on purpose. DigiByte’s Odocrypt changes its algorithm every ten days, which an FPGA can follow with a new bitstream and an ASIC cannot.

2026: dusting off the Spartans

Which brings us to now. Proxima’s switch to BLAKE2b in November 2026 produced exactly the kind of algorithm FPGAs love: pure 64-bit arithmetic and no big memory. So we built bitstreams, and we have released the host software and the ZTEX proof-of-concept bitstream to the public as suprminer-fpga. Fifteen-year-old boards that last earned their keep on Bitcoin in 2012 are mining again. There is something rather wonderful about that.

Chapter VI: Where FPGAs are the wrong tool, part one: memory

Here is the catch, and it is a big one. Remember the on-chip memory from Chapter II? A big FPGA such as the VU9P has a few tens of megabytes of it. That is plenty for hashing state. It is hopeless for a memory-hard algorithm.

Memory-hard algorithms are designed so that each hash needs lots of data that you can’t compute on the fly and therefore have to fetch. Ethash (the old Ethereum algorithm), KawPoW (Ravencoin), Autolykos and the various DAG-based hashes like the one Keryx uses work over a dataset of several gigabytes, reading from random places in it all the time (we wrote a whole explainer on DAGs if you fancy it). Speed on these algorithms is decided by memory bandwidth, not by logic.

And memory bandwidth is the one thing a gaming GPU has in obscene quantities. A modern high-end card moves well over a terabyte per second through its GDDR memory. An FPGA’s fabric can be as clever as it likes; if it is sitting idle waiting for data, it isn’t hashing.

“But what about FPGA boards with memory?”

Good question, and the industry tried. Some boards added DDR4 (too slow for this job), and the serious attempts went for HBM, the stacked high-bandwidth memory used on datacentre accelerators: cards built around HBM-equipped Virtex parts and Xilinx’s own Alveo HBM cards. They could mine Ethash, and some did so respectably. But with a few hundred gigabytes per second of bandwidth, and a price tag in the thousands, they were never going to embarrass a GPU, which brings a terabyte per second for a fraction of the cost and can be resold to a gamer afterwards. On a memory-bound algorithm the FPGA’s clever logic is a Formula 1 engine bolted to a garden hose.

Chapter VII: Where FPGAs are the wrong tool, part two: RandomX and the CPU coins

Then there are the algorithms that were designed from the ground up for one particular kind of chip: the one already in your computer. The best-known is RandomX, which Monero has used since 2019.

RandomX doesn’t hash in the usual sense. For every hash it generates a random program and runs it in a virtual machine. Those programs use integer and floating-point arithmetic, including double-precision maths with different rounding modes, along with branches and AES instructions. They read and write a scratchpad sized to fit snugly into a CPU’s caches, and pull data from a 2 GiB dataset. Every one of those choices is deliberate. RandomX’s designers set out to make the “ideal RandomX ASIC” look exactly like a modern CPU, with its branch predictors, out-of-order execution, big caches and fast floating point.

So what would an FPGA have to do? Essentially, build a CPU out of LUTs and flip-flops. Soft processors on FPGAs exist, but they run at a few hundred megahertz, while the chip in your desktop runs at four or five gigahertz with decades of microarchitecture behind it. It is like trying to beat a Rolls-Royce with a self-assembly kit car: technically possible to build, but you will be overtaken on the slip road.

That is why FPGAs play essentially no role in Monero mining, and why CPUs are still the right tool there. The same goes, more or less, for other CPU-oriented algorithms. Our CPU mining guide has the current list.

Chapter VIII: “It looks complicated”, or: is it really?

A decade ago, honestly, yes. Today, much less so, at least on the ZTEX boards. The ZTEX 1.15y has its own USB controller, so the whole procedure is:

1. Plug the board into USB and power. No PCIe riser, no 1,000 W power supply, no BIOS settings.
2. Build suprminer-fpga (it is a normal CMake project for Linux, and the README walks you through it).
3. Run it with --program --selftest once. It loads the bitstream into all four FPGAs and checks every core against known answers.
4. Point it at a pool and mine.

# program all attached ZTEX boards and run the built-in self-test
./suprminer-fpga -a proxima --fpga ztex --program --selftest

# mine Proxima (replace the placeholders with your own details)
./suprminer-fpga -a proxima --fpga ztex --account my-account.json \
    --worker rig1 -o stratum+tcp://POOL:PORT

Every hit the FPGA reports is re-hashed by the host before it is submitted, so a flaky board shows up as a hardware error in the log instead of as rejected shares. The miner works on proxi.suprnova.cc and on any other pool that implements the open Suprnova stratum.

The VU9P cards are more of a hobbyist’s project: they are PCIe cards, so they need a host machine, proper cooling and JTAG programming, and the core voltage has to be set before loading the bitstream. The miner handles most of it, but it isn’t a plug-in-and-go-to-the-pub affair. Faster ZTEX images (including the 124 MHz one) and VU9P bitstreams are available on request; see the repository.

Chapter IX: The verdict, with the kettle on

So, is a GPU “just much better”? The honest answer is the one every engineer gives and every journalist hates: it depends.

• Per chip and per watt, on a compute-only hash, a well-built FPGA design wins against a GPU from the same era by a lot, and a ten-year-old VU9P still beats a brand-new RTX 5090 by about two to one.
• An old Spartan-6 board loses to a modern GPU on efficiency, but it costs 25 W, makes no noise and was probably gathering dust anyway. For the boards people already own, that is a happy ending.
• On memory-hard algorithms, GPUs win thanks to their memory bandwidth, even against FPGA boards with HBM.
• On RandomX, your CPU wins, which was rather the point.
• And whenever enough money piles up on a simple algorithm, an ASIC will eventually turn up, and it will have been prototyped on an FPGA.

FPGAs are not magic and they are not the future of all mining. They are the chip you reach for when an algorithm is simple enough to be turned into wiring, valuable enough to be worth a bitstream, and young enough that nobody has spent millions freezing it into silicon. Proxima, right now, ticks all three boxes. And there is a particular pleasure, we must admit, in watching a board that last mined Bitcoin when Gangnam Style was in the charts quietly submit shares again.